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1 publication order number : lv52130n0xa_4xa/d www.onsemi.com ? semiconductor component s industries, llc, 2015 october 2015 - rev. 0 ordering information see detailed ordering and shipping info rmation on page 19 of this data sheet. lv52130n0xa lv52130n4xa overview the lv52130n0xa and lv52130n4xa are dual-output with 1coil boost dc-dc converter and built-in inverter charge pump circuit. feature ? 1 coil dual-outputs ? vout1 output (+5v/+5.4v) ? vout2 output (-5v/-5.4v) ? operating voltage from 2.5v to 5.5v ? each output voltages adjusted by i2c ? synchronous rectification ? scp(vout1 to gnd / vout2 to gnd) typical applications lcd / amoled panel power supply bi-cmos ic 1coil boost dc-dc converter and inverter charge pump wlp15 - 0.4mm pitch (1.55mm ? 2.15mm, amax=0.625mm) fig.1 application * i 2 c bus is a trademark of philips corporation.
lv52130n0xa/4xa www.onsemi.com 2 specifications lv52130n0xa default: vout1=+5v, vout2=?5v marking: 130nx ymxx lv52130n4xa default: vout1=+5.4v, vout2=?5.4v marking: 130n4 ymxx absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit maximum su pp l y volta g e vinmax vin to gnds +6 v maximum pin volta g e1 v p in1max cn , vout2 to gnds -6 v maximum pin volta g e2 v p in2max lx +7 v maximum pin volta g e3 v p in3max other p in to gnds +6 v allowable p owe r dissi p ation pdmax ta=25c the s p ecified board*1 1 w o p eratin g tem p erature to pr ? 40 to +85 c stora g e tem p erature tst g ? 55 to +125 c *1 mounted on a specified board: 50 mm50mm1mm (2 layer glass epoxy) caution 1) absolute maximum ratings represent the valu es which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of absolute maximum ratings, as a re sult of continuous usage under hig h temperature, high current, high voltage, or drastic temperatur e change, the reliability of the ic may be degraded. please contact us for the further details. recommended operating conditions at ta = 25 ? c parameter symbol conditions ratings unit supply voltage range v in o p vin 2.5 to 5.5 v electrical characteristics at ta ? 25 ? c, pvin=vin=3.7v vout1=5v vout2=-5v (unless otherwise noted) parameter symbol conditions ratings unit min typ max vin current standby current dissipation icc1 ic disable 8.5 ua vbst dcdc converter vbst current limit iclbst lx 0.9 1.2 1.5 a vout1 ldo vout1 voltage vout1 default 5 v vout1 voltage range vout1 100mvsteps by i2c 4.1 5.7 v vout1 voltage accuracy vout1 ?1 1 % vout1 dropout voltage vdrop 150ma 150 mv vout1 current iout1 iout2=0 200 ma vout1 line regulation vlinr1 dvo=1v io=30ma 0.3 %/v vout1 load regulation vldr1 io=2ma/150ma 4 mv discharge resistance 1 rvo1 70 ? soft-start tssvo1 0.2 ms continued on next page stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lv52130n0xa/4xa www.onsemi.com 3 continued from preceding page. parameter symbol conditions ratings unit min typ max vout2 charge pump vout2 voltage vout2 default -5 v vout2 voltage range vout2r 100mv steps by i2c ?5.7 ?4.1 v v out2 voltage accuracy vout2a -1 1 % vout2 current iout2 iout1=0 100 ma vout2 line regulation vlinr2 dvo=1v io=30ma 0.3 %/v vout2 load regulation vldr2 io=2ma/60ma 20 mv discharge resistance 2 rvo2 20 ? soft-start tssvo2 0.2 ms osc osc frequency1 fosc1 boost-dcdc 1.48 1.85 2.22 mhz osc frequency2 fosc2 charge pump 0.74 0.925 1.11 mhz uvlo uvlo up vuvlo_h vin up 2.5 v uvlo down vuvlo_l vin down 2.3 v control input high level input voltage vinh sda/scl/en1/en2 1.26 vin v low level input voltage vinl sda/scl/en1/en2 0 0.54 v pulldown resistance rpd en1/en2 400 k ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lv52130n0xa/4xa www.onsemi.com 4 package dimensions unit : mm lv52130n0xa/lv52130n4xa is as follows. wlcsp15, 2.15x1.55 case 567hy issue a seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 2.15 bsc e b 0.20 0.30 e 0.40 bsc 0.625 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.08 c 15x b c b a 0.10 c a1 a c 0.16 0.26 1.55 bsc 0.20 15x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.05 c 2x top view side view bottom view note 3 e recommended package outline 123 pitch d e pitch a1 = device mark xx = assembly lot code ( ) marking diagram top view
lv52130n0xa/4xa www.onsemi.com 5 block diagram fig.2 block diagram pin function pin # pin name description a1 en2 enable1 input pin a2 vout2 vout2 output pin a3 cn flying capacitor connection pin for charge pump b1 en1 enable1 input pin b2 scl i2c clock signal input pin b3/e1 pgnd power ground c1 vin power supply voltage c2 sda i2c data signal input / output pin c3 cp flying capacitor connection pin for charge pump d1 lx boost converter switching pin d2 sgnd signal ground d3/e2 vbst boost converter direct output pin e3 vout1 vout1 output pin
lv52130n0xa/4xa www.onsemi.com 6 pin connections top view bottom view pd-max mounted on a specified board: 50mm50mm1mm (2 layer glass epoxy) ambient temperature c allowable power dissipation pd-max [w]
lv52130n0xa/4xa www.onsemi.com 7 fig.3 recommendation applications table . component list for typical characteristics circuit reference description manufacturer and part number c 2.2f, +-10%, 10v, x5r, ceramic tdk - c1608x5r1a225k 4.7f, +-10%, 10v, x5r, ceramic tdk - c1608x5r1a475k 10f, +-10%, 10v, x5r, ceramic tdk - c1608x5r1a106k l 2.2h, 1.1a, 120m ? , 2.5mm ? 2.0mm ? ? , 2.5mm ? 2.0mm ?
lv52130n0xa/4xa www.onsemi.com 8 bitmap ( i2c control ) / i2c disable at standby write: ic address : 0111110x x=0:write mode / x=1:inhibition sub address msb lsb (7) (6) (5) (4) (3) (2) (1) (0) vout1 0000 0000 - - - vout1 vout1 vout1 vout1 vout1 vout2 0000 0001 - - - vout2 vout2 vout2 vout2 vout2 mode 0000 0011 no use no use note: about sub address ?0000 0011? prohibit data's setting ?0? of data (0) and data (1). bits vout1 [v] vout2 [v] 0 not use not use 1 4.1 -4.1 2 4.2 -4.2 3 4.3 -4.3 4 4.4 -4.4 5 4.5 -4.5 6 4.6 -4.6 7 4.7 -4.7 8 4.8 -4.8 9 4.9 -4.9 10 5.0* -5.0* 11 5.1 -5.1 12 5.2 -5.2 13 5.3 -5.3 14 5.4** -5.4** 15 5.5 -5.5 16 5.6 -5.6 17 5.7 -5.7 * :default = +-5v ( lv52130n0xa ) ** :default = +-5.4v ( lv52130n4xa )
lv52130n0xa/4xa www.onsemi.com 9 serial bus communication specifications standard mode parameter symbol condit ions min typ max unit scl clock frequency fscl scl clock frequency 0 - 100 khz data set up time ts1 scl setup time re lative to the fall of sda 4.7 - - s ts2 sda setup time relative to the rise of scl 250 - - ns ts3 scl setup time relative to the rise of sda 4.0 - - s data hold time th1 scl data hold time relative to the rise of sda 4.0 - - s th2 sda hold time re lative to the fall of scl 0 - - s pulse width twl scl pulse width for the l period 4.7 - - s twh scl pulse width for the h period 4.0 - - s input waveform conditions ton scl and sda (input) rise time - - 1000 ns tof scl and sda (input) fall time - - 300 ns bus free time tbuf time between stop and start conditions 4.7 - - s high-speed mode parameter symbol condit ions min typ max unit scl clock frequency fscl scl clock frequency 0 - 400 khz data setup time ts1 scl setup time re lative to the fall of sda 0.6 - - s ts2 sda setup time relative to the rise of scl 100 - - ns ts3 scl setup time relative to the rise of sda 0.6 - - s data hold time th1 scl data hold time relative to the rise of sda 0.6 - - s th2 sda hold time re lative to the fall of scl 0 - - s pulse width twl scl pulse width for the l period 1.3 - - s twh scl pulse width for the h period 0.6 - - s input waveform conditions ton scl and sda (input) rise time - - 300 ns tof scl and sda (input) fall time - - 300 ns bus free time tbuf time between stop and start conditions 1.3 - - s i 2 c serial transfer timing conditions
lv52130n0xa/4xa www.onsemi.com 10 input waveform condition i 2 c control transmission method in start and stop conditions of the i 2 c bus, sda should be kept in the constant state while scl is "h" as shown below during data transfer. when data transfer is not made, both scl and sda are in the "h" state. when scl = sda="h", change of sda from "h" to "l" enables the start conditions to start access. when scl is "h", change of sda from "l" to "h" enables the stop conditions to stop access.
lv52130n0xa/4xa www.onsemi.com 11 data transfer and acknowledgement response after establishment of start conditions, da ta transfer is made by one byte (8 bits). data transfer enables continuous transfer of any number of bytes. each time of the 8-bit data is transferred, the ack signal is sent from the receive side to the send side. the ack signal is issued when sda(on the send side) is released and sda(on the receive side) is set "l" immediately after fall of the clock pulse at the scl eighth bit of data transfer to "l". when the next 1-byte transfer is left in the receive state after transmission of the ack signal from the receive side, the receive side releases sda at fall of the scl ninth clock. in the i2c bus, there is no ce signal. inst ead, 7-bit slave address is assigned to each device and the first byte of transfer is assigned to the command (r/w) representing the 7-bit slave address and subsequent transfer direction. note that only write is valid in this ic. the 7-bit address is transferred sequentially from msb and the eighth bit is "l" representing write. input 1data input 2data (register address auto increment)
lv52130n0xa/4xa www.onsemi.com 12 detailed descriptions the lv52130nx has dual-output vout1 (ldo) and vout2 (bu ilt-in inverter charge pump) with 1coil boost dcdc converter. both outputs are separately controlled by i2c control and pin en1/en2. boost converter is a fixed-frequency pulse width modulated (pwm) re gulator. at rated load, each converter operate s at continuous con duction mode (ccm). at light loads, both converters can enter in discontinuous conduction mode (dcm). cycle-by-cycle peak current limit and thermal provide value added feat ures to protect the device. inductor selection three different electrical parameters need to be cons idered when selecting an inductor, the value of the inductor, the saturation current and the dcr. during normal and heavy load operation, the lv52130nx is intended to operate in continuous conduction mode (ccm). the equation below can be used to calculate the peak current. ipeak_p = iout1 / (n1 x ( 1- d1 )) + ( vin x d1 ) / 2 x l1 x fosc1 vin:battery voltage, iout1:load current, l:inductor valu e, fosc1: osc frequency1, d1:duty cycle, n1:converter efficiency varies with load current. a good approximation is to use = 0.85. it is important to ensure that the inductor current rating is high enough such that it not saturate. as the inductor size is reduced, the peak current for a given set of conditions increases along with higher current ripple so it is not possibl e to deliver maximum output power at lowe r inductor values. finally an acceptable dcr must be selected regarding losses in the coil and must be lower than 250 m ? (typical) to limit excessive voltage drop. in addition, as dcr is reduced, overall efficiency will impr ove. the inductor value is recommended to use a 4.7 h or 2.2h. por function this is ?power on reset? function to reset internal logi c circuits which include scp?s latch. this function can be worked by reducing ic?s vin voltage until about 1v.
lv52130n0xa/4xa www.onsemi.com 13 #2 operations to power off data send (5.0v)(*4) power off ( en1/en2:lo )( *5 ) #1 operation to power on power on (en1/en2:hi)(*1) operation after 45ms (until vout1&2 becomes stable)(*2) data send (5.5v or 5.7v)(*3) +5.5v to +5.7v -5.5v to -5.7v +5.2v +5.7 to +5.9v vin en1 /en2 i2c vbst vout1 vout2 45ms 45ms (*3)0x0for11 (*4)0x0a default (*3)0x0for11 (*4)0x0a default +5.2v +5.7 to +5.9v +5.0v +5.5v to +5.7v -5.0v -5.5v to -5.7v >0s >0s 40ms (*1)power-on (*1)power-on (*5)power-off (*5)power-off (*2)operation (*2)operation +5.0v -5.0v +5.0v -5.0v start/shutdown sequencing enable input (pin en1/en2) is used as enable input logic. an active high logic level on this pin enables the device. a built-in pull-down resistor disables the device if the pin is le ft open. if a high logic signal is applied, the lv52130nx start s with timing sequence as depicted figure 4. it must be kept below points in the start/shutdown sequence for stable operation. ? when vout set 5.5v vout1 / vout2 -5.5v, please change to its voltage 45msec later. ? about shutdown, please send default (5.0v/5.4v) data by iic before en=off. ? the each load current of vout1 an d vout2 while startup is only char ging current for the each external capacitor (4.7f). ? ic needs 55msec waiting time from the en1 until loading of panel module. ? keep each the h/l levels at lease 1msec fig.4 sequencing diagram (c) in the case of LV52130N0XA-VH (b) en on separately (a) en on simultaneously vin 1ms vbst vout1 vout2 en1 en2 200us vin vbst vout1 vout2 en1 en2 40ms 1ms 40ms load allowed load allowed 55ms 55ms 50ms to 54ms 200us 200us
lv52130n0xa/4xa www.onsemi.com 14 ocp and scp function ic has ocp and scp function and the behavior is shown in figures below. (1) ocp limit transition in normal operation the ocp means ?over current protection? and is equipped for preventing excessive inrush current about vout1. it watches for limit of 150ma during 300usec from ramp up of vout1, and then changes almost free. (2) heavy load of during ramp up if vout1 voltage doesn?t reach target voltage at the end of time of the 300usec, then ic is doubtful of excessive current load and changes the limit to 25ma. this small current is he ld until recovery of the vout1 voltage. by way of example of a case, if high load current like as 25ohm that is bigger th an 150ma current capacity of vout1 comes during ramp up term and after 300usec at vout1, then ic chooses 25ma mode which is defeated the load. as a result, ic goes to off with latch and requires vin?s re-installation. as it was mentioned in start/shutdown sequencing section above, the 55msec waiting time is needed to avoid the case.
lv52130n0xa/4xa www.onsemi.com 15 (3) scp function the scp means ?short circuit protection?. this is used to protect each vout when they are connected to the gnd. scp function becomes active when vout voltage reaches under 60% of its target volta ge. once scp is activated, the counter begins to count 10msec. if the scp detection is active for full 10msec, ic then gets shut down and latch. on the other hand, if the vout voltage is recovered within this 10msec ic will reactivate. this latch is released by dropping vin.
lv52130n0xa/4xa www.onsemi.com 16 startup shutdown sequence summary when vout set 5.5v vout1 / vout2 -5.5v for start up (1) en1=h ; (2) 45msec later, send i2c wish data; (3) after 50msec from (1), en2=h; (4) 55msec later, start panel load; for shut down (1) stop panel load (2) send i2c data of 0x0a; (3) en1 and en2 = l; note: need spacing over 1ms until the next en1=h or en2=h from ?(3) en1 and en2=l?.
lv52130n0xa/4xa www.onsemi.com 17 typical operating characteristics efficiency efficiency load regulation vout1 load regulation vout1 load regulation vout2 load regulation vout2 vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=4.7f, cbst=4.7f, cc p_ cn=2.2 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7f, cvout2=4.7f, cbst=4.7f, cc p_ cn=2.2 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=4.7f, cbst=4.7f, cc p_ cn=2.2 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7f, cvout2=4.7f, cbst=4.7f, cc p_ cn=2.2 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=4.7f, cbst=4.7f, cc p_ cn=2.2 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7uf, cvout2=4.7uf, cbst=4.7uf, cc p_ cn=2.2uf, cvin=10uf+4.7uf, l=4.7uh
lv52130n0xa/4xa www.onsemi.com 18 typical operating characteristics efficiency efficiency load regulation vout1 load regulation vout1 load regulation vout2 load regulation vout2 vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=2.2 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=2.2 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=4.7 h vout1=5v, vout2=-5v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=2.2 h vout1=5.4v, vout2=-5.4v (iout=vout1 to vout2) cvout1=4.7f, cvout2=10f, cbst=10f, cc p_ cn=4.7 f, c v i n = 1 0 f+4.7 f, l=4.7 h
lv52130n0xa/4xa www.onsemi.com 19 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. ordering information device package shipping (qty / packing) LV52130N0XA-VH wlp15 (1.55 ? 4000 / tape & reel lv52130n4xa-vh wlp15 (1.55 ?

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